As semiconductor devices become smaller, it becomes necessary to arrange individual components within a device such that minimal separation distances are achieved. The need to design compact component arrangements occurs most significantly in memory devices. Because of the large number of components needed to fabricate a typical dynamic-random-access-memory device (DRAM), or static-random-access-memory device (SRAM), the components must be arranged compactly if the overall device dimensions are not to become excessively large. This problem is especially critical in SRAM devices where a typical individual memory cell contains as many as six separate components. Simple down-sizing of components can only be pursued to the limit of the line-width definition capability of the manufacturing process. Once the line-width definition limits are reached, new design methodology must be employed if further reduction in memory cell area is to be achieved.
One technique for reducing memory cell dimensions, is to place a number of the components in a trench structure, which is sunk into the substrate. However, even with the integration of a trench structure into the memory cell, additional surface area is still necessary for component connections. For example, active surface regions of the cell must be available for the formation of cell nodes. Typically, the formation of cell nodes requires that surface area of electrically conductive layers be exposed by openings in overlying insulating layers. Contact metallization is placed in openings to provide a means of electrically coupling cell interconnects and components together. Depending on the number of components to be electrically coupled together, the formation of the contact can require elaborate metallization structures. In the case of an SRAM memory cell, a structure known in the art as a shared contact, or buried contact, serves to electrically couple the inverters and the pass transistors. The inclusion of a complex, shared contact structure into an SRAM memory cell increases the total amount of substrate surface area needed to fabricate the cell.
The further reduction in substrate surface area required to form a memory cell is limited by the use of conventional contact metallization structures. While development of new methods for interconnecting cell components is needed, the improvement cannot be attained at the expense of cell performance. In particular, SRAM memory cells suffer stability problems as cell size is reduced. To function properly, the SRAM memory cell, when charged, must hold a voltage level, either high (logic 1) or low (logic 0). When reading data from the cell, the charge pulse generated as the pass transistor turns on must not flip the voltage level at the output nodes. Usually this problem is controlled by adjusting the width-to-length (W/L) ratios of the driver transistor relative to the pass transistor. Typically, the channel width (W) is set and the channel length (L) of each transistor is adjusted. Higher cell stability is obtained when the L value of the pass transistors is larger than the L value of the driver transistor. The ratio of the W/L values of the two transistors is known as -the cell ratio and is commonly specified to be at least 3.0 or larger. Care must be taken in the design of a memory cell to interconnect cell components in such a way as to avoid a degradation in cell stability. Therefore, additional development of memory cell technology requires that an improved interconnect structure be achieved while not impairing cell stability.